The present invention relates to communication systems, and more particularly to a communication path that includes one or more latency-aligning transceivers.
FIG. 1 illustrates a prior art memory system that includes multiple integrated circuit memory devices 120 coupled to a memory controller 110 via a bidirectional communication channel 140. Because each memory device 120 consumes physical space along the channel, the number of memory devices that can be coupled to the channel 140, and to some extent the storage capacity of the memory system, is limited by the length of the channel 140. The length of the channel 140 is itself limited by a number of practical considerations. For example, signals attenuate as they propagate down the channel 140, constraining the channel length to one that provides a tolerable signal level at the memory IC farthest from the controller 110. Similarly, channel capacitance increases with channel length, limiting the frequency response of the channel. Accordingly, the channel length usually must be limited to support the desired operating frequency of the memory system.
One technique for increasing the number of memory devices that can be used in a memory system without unacceptable loss in signaling margin or frequency response is to use buffering circuits to segment the communication path into multiple smaller channels. Unfortunately, buffers add latency that can be problematic, particularly in synchronous memory systems which rely on deterministic timing relationships. For example, in some memory systems, memory operations are pipelined by transmitting commands in the intervening time between transmission of an earlier command (e.g., a read command) and responsive transmission of the corresponding data (e.g., the read data). When buffers are positioned along the channel""s length, however, the time intervals between command and response transmissions vary arbitrarily depending on the positions of the addressed memory devices (i.e., memory devices positioned downstream from one or more buffers or repeaters exhibit greater effective response delay than memory devices coupled directly to the memory controller). This significantly complicates command pipelining.
Thus, it is desirable to provide a memory subsystem that can support a large number of memory devices without degrading the reliability and performance of the memory system.
A memory system including one or more transceivers with latency alignment circuitry is disclosed in various embodiments. The memory system includes a communication path that is segmented into a primary channel and one or more stick channels by appropriate placement of the latency aligning transceivers. In one embodiment, the transceivers buffer clock, control and data signals while also aligning the latency in the round-trip path between the memory controller and the stick channel driven by the transceiver to a clock cycle boundary. When memory devices that have adjustable response delays are coupled to the different stick channels in the memory system, the memory system can be configured so that the total response latency is substantially the same for each memory IC in the memory system. This simplifies command pipelining significantly, permitting commands to be packed densely within the available channel bandwidth. As discussed below, stick channels themselves can feed one or more additional transceivers, making any number of interconnection topologies possible.
These and other features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows.